The present invention relates in general to data processing systems, and in particular, to the translations of addresses in a processor.
Data processing systems employ operating systems (xe2x80x9cOS""sxe2x80x9d) capable of running several individual programs concurrently. These programs are often run using virtual addressing. The reasons for using virtual addressing (e.g., efficient use of real memory) are well known in the art.
In such a system, each program has access to the full 64-bit effective address (EA) space, and the virtual address (VA) space must be larger (e.g., 80 bits) so the operating system can allocate separate regions of the virtual address space to each program. The operating system normally associates some regions of this 64-bit effective address space with private virtual address space regions for exclusive use by a program when the program is started. None of these regions are accessible to a second program. Other regions of this effective address space are associated with shared virtual address space regions that are accessible to some or all other programs. These shared regions normally contain parts of the operating system and subroutine libraries.
When a load or store instruction is executed, or an instruction is to be fetched, the effective address must be translated to a virtual address and then to a real address (RA) before memory can be accessed. Translating the effective address to a virtual address is often performed using a segment-lookaside-buffer (SLB) or a segment register, the content of which replace some of the high-order bits of the effective address. The resulting virtual address is subsequently translated to a real address by the processor when it searches the translation-lookaside-buffer (TLB) or the page table. The TLB is a cache of the content of page table entries that have been used recently to translate virtual addresses.
As a result of the increase of the frequencies at which processors run and the growth in size of TLB arrays, performing the two step process of address translation can significantly reduce the performance of the processor. To reduce the performance penalty associated with address translation, the processor uses one or more lookaside-buffer mechanisms (ERATs) to translate effective addresses directly to real addresses. These arrays are caches that contain the results of recent translations of effective addresses to real addresses. Because ERAT arrays are smaller than TLB arrays, they are faster and the use of ERAT arrays avoids the intermediate translation step.
Referring to FIG. 4, when a program 403 is executed, program 403 will occupy only a subset of the memory space allocated by the OS 401. Additionally, common libraries 402 used by a plurality of programs 403 will also require a certain amount of the memory space. When a new program is loaded, the contents of some SLB entries are altered. This will change the relationship between the effective addresses and the virtual addresses. Consequently, the effective address to real address translations associated with the replaced program within the ERATs become stale. When such a change in the entries in the SLB occur, there is no way to find the exact corresponding entries within the ERATs. Thus, the prior art has simply invalidated all of the ERATs"" entries. The problem with such a solution is that there may be entries within the ERATs that pertain solely to the OS 401 or the common libraries 402. If all the entries in the ERATs are invalidated, then those entries pertaining to the OS 401 and the libraries 402 are also invalidated. This can harm the efficiency and the speed of the microprocessor, because now new entries pertaining to the OS 401 and the libraries 402 will have to be entered into the ERATs, instead of the microprocessor being able to continue using the previous entries.
Therefore, there is needed in the art a system and method for invalidating a subset of ERAT entries.
The present invention addresses the foregoing need by providing a system and method for selectively invalidating a subset of the ERAT in load/store and instruction fetching units of a microprocessor. One or more Class bits are associated with each entry in the segment lookaside buffer. Then, when such an entry in the SLB is invalidated, a message is sent to the ERAT to selectively invalidate any corresponding entries therein. This may be performed by using a CAM compare of the received Class bit(s) with entries in the ERAT.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.